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Dual RF LDMOS Bias Controllers
with I 2 C/SPI Interface
Typical Operating Circuit (I 2 C Mode)
5V
5V
EXTERNAL
DV DD
GATEV DD
AV DD
REFDAC REFADC
REFERENCE
DRAIN
SUPPLY
SCL
SCL
SDA
MICROCONTROLLER
SDA/DIN
ALARM
BUSY
SAFE2
CS1+
CS1-
C F *
R F *
SAFE1
+5V
GATE1
A0/CSB
MAX1385
DGND
A1/DOUT
A2/N.C.
MAX1386
RF INPUT
RF
OUTPUT
SEL
OPSAFE1
OPSAFE2
ADCIN1
(AT LDMOSFET)
CNVST
ADCIN2
DRAIN
SUPPLY
DXP1
CS2+
DXN1
C F *
5V
(AT LDMOSFET)
DXP2
CS2-
R F *
DXN2
GATE2
PGAOUT1 PGAOUT2
AGND
GATEGND
RF
OUTPUT
RF INPUT
*SELECT R F AND C F BASED ON DESIRED FILTER CUT-OFF FREQUENCY.
LIMIT R F TO MINIMIZE OFFSET ERRORS.
50
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